The disclosures herein relate generally to processors, and more specifically, to processors that employ register recovery mechanisms after flush operations.
Modern information handling systems (IHSs) may track dependencies between instructions by using reservation station (RS) and recovery buffer units (RBU)s. Because out-of-sequence instruction handling is common in modern IHSs, processors typically track the dependencies between younger instructions and older instructions. If younger instructions depend on the results of older instructions, those younger instructions cannot complete until the results for the older instructions are available. During instruction dispatch, a general purpose register (GPR) may provide register A/register B (RA/RB) operand information that the reservation station (RS) receives. The recovery buffer unit (RBU) receives target register (RT) information from the GPR. The GPR may include all information that younger instructions need to track in case a younger instruction is dependent upon an older instructions execution results.
In the case of a flush operation, such as instruction branch flush, the IHS typically will recover to a state prior to the flush operation. The processor reads the RBU and moves data to the GPR to restore the GPR to a state or point prior to the flush. The instruction dispatch process may not resume until the GPR completely recovers from the flush event. In the case where multiple instructions write to the same target register (RT) location in the GPR, the recovery buffer unit (RBU) will contain multiple entries that reference the same target register (RT) location. During a flush there will be multiple RBU entries to read out of the recovery buffer unit (RBU) to restore a particular target register (RT) location with the proper data prior to the flush.